| commit | fff35d45e16fae125c6000cb87e254cb634ac7fb | [log] [tgz] |
|---|---|---|
| author | Sakari Ailus <sakari.ailus@linux.intel.com> | Sat Mar 02 10:23:12 2019 -0500 |
| committer | Mauro Carvalho Chehab <mchehab+samsung@kernel.org> | Wed Mar 20 06:35:20 2019 -0400 |
| tree | 9f88a31a2923ed9bb53bcf0be43a0ebfe8ca7499 | |
| parent | 9d3863736a267068a0ae67c6695af8770ef330b7 [diff] |
media: v4l2-fwnode: The first default data lane is 0 on C-PHY
C-PHY has no clock lanes. Therefore the first data lane is 0 by default.
Fixes: edc6d56c2e7e ("media: v4l: fwnode: Support parsing of CSI-2 C-PHY endpoints")
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>