tree d6f9907076138f33db9691e28d8b6bcfded1a214
parent 407254da291c03c32109881ca8cbda5607714a8f
author Bill Huang <bilhuang@nvidia.com> 1434662906 -0400
committer Thierry Reding <treding@nvidia.com> 1448039104 +0100

clk: tegra: pll: Add code to handle if resets are supported by PLL

If a PLL has a reset_reg specified, properly handle that in the
enable/disable logic paths.

Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>