| commit | fc5db58539b49351e76f19817ed1102bf7c712d0 | [log] [tgz] |
|---|---|---|
| author | Kai-Heng Feng <kai.heng.feng@canonical.com> | Wed Oct 16 18:38:16 2019 +0800 |
| committer | Thomas Gleixner <tglx@linutronix.de> | Tue Nov 12 15:55:20 2019 +0100 |
| tree | 07aeb9357412b8cc139f1aeba853e2482ac6fde9 | |
| parent | 31f4f5b495a62c9a8b15b1c3581acd5efeb9af8c [diff] |
x86/quirks: Disable HPET on Intel Coffe Lake platforms Some Coffee Lake platforms have a skewed HPET timer once the SoCs entered PC10, which in consequence marks TSC as unstable because HPET is used as watchdog clocksource for TSC. Harry Pan tried to work around it in the clocksource watchdog code [1] thereby creating a circular dependency between HPET and TSC. This also ignores the fact, that HPET is not only unsuitable as watchdog clocksource on these systems, it becomes unusable in general. Disable HPET on affected platforms. Suggested-by: Feng Tang <feng.tang@intel.com> Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: stable@vger.kernel.org Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=203183 Link: https://lore.kernel.org/lkml/20190516090651.1396-1-harry.pan@intel.com/ [1] Link: https://lkml.kernel.org/r/20191016103816.30650-1-kai.heng.feng@canonical.com