| commit | fc2de40986f5a35c02f06dea4221113b3a7a7c3c | [log] [tgz] |
|---|---|---|
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | Fri Jan 25 21:44:41 2013 +0200 |
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | Sat Jan 26 17:29:45 2013 +0100 |
| tree | 5dda4cb528b994e35bca8674c4e28848cf69bfe2 | |
| parent | fba5d532d16db812dabaa80fb7570820daa2707b [diff] |
drm/i915: PLL registers need an offset on VLV v2: Dropped the clock gating registers Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>