| commit | fab3833338779e1e668bd58d1f76d601657304b8 | [log] [tgz] |
|---|---|---|
| author | Thinh Nguyen <Thinh.Nguyen@synopsys.com> | Fri Mar 16 15:33:48 2018 -0700 |
| committer | Felipe Balbi <felipe.balbi@linux.intel.com> | Thu Mar 22 10:48:46 2018 +0200 |
| tree | a7071ba2b0f8b27bfadc3600040378fdf2b5bd65 | |
| parent | cabdf83dadfb3d83eec31e0f0638a92dbd716435 [diff] |
usb: dwc3: Add SoftReset PHY synchonization delay From DWC_usb31 programming guide section 1.3.2, once DWC3_DCTL_CSFTRST bit is cleared, we must wait at least 50ms before accessing the PHY domain (synchronization delay). Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>