| commit | fa4127c5eb8def998fd8a471d51a4f2560dea0a2 | [log] [tgz] |
|---|---|---|
| author | Giulio Benetti <giulio.benetti@micronovasrl.com> | Thu Feb 15 18:54:48 2018 +0100 |
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | Fri Feb 16 21:16:03 2018 +0100 |
| tree | e463a25d2caa1c25a2576205f50c4c5848b8ba51 | |
| parent | cd0e93d865538decfd0f917c112d3fc57aac90fe [diff] |
drm/sun4i: fix HSYNC and VSYNC polarity Differently from other Lcd signals, HSYNC and VSYNC signals result inverted if their bits are cleared to 0. Invert their settings of IO_POL register. Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/1518717288-123578-1-git-send-email-giulio.benetti@micronovasrl.com