[SPARC64]: Proper multi-core scheduling support.
The scheduling domain hierarchy is:
all cpus -->
cpus that share an instruction cache -->
cpus that share an integer execution unit
Signed-off-by: David S. Miller <davem@davemloft.net>
diff --git a/include/asm-sparc64/topology.h b/include/asm-sparc64/topology.h
index e0d450d..4880f7c 100644
--- a/include/asm-sparc64/topology.h
+++ b/include/asm-sparc64/topology.h
@@ -1,12 +1,19 @@
#ifndef _ASM_SPARC64_TOPOLOGY_H
#define _ASM_SPARC64_TOPOLOGY_H
+#ifdef CONFIG_SMP
#include <asm/spitfire.h>
-#define smt_capable() (tlb_type == hypervisor)
+
+#define topology_physical_package_id(cpu) (cpu_data(cpu).proc_id)
+#define topology_core_id(cpu) (cpu_data(cpu).core_id)
+#define topology_core_siblings(cpu) (cpu_core_map[cpu])
+#define topology_thread_siblings(cpu) (cpu_sibling_map[cpu])
+#define mc_capable() (tlb_type == hypervisor)
+#define smt_capable() (tlb_type == hypervisor)
+#endif /* CONFIG_SMP */
#include <asm-generic/topology.h>
-#define topology_core_id(cpu) (cpu_data(cpu).core_id)
-#define topology_thread_siblings(cpu) (cpu_sibling_map[cpu])
+#define cpu_coregroup_map(cpu) (cpu_core_map[cpu])
#endif /* _ASM_SPARC64_TOPOLOGY_H */