| commit | f5337346cd8fe1b105f319b4b7fb06fe25c54480 | [log] [tgz] |
|---|---|---|
| author | Florian Fainelli <f.fainelli@gmail.com> | Thu Apr 20 12:05:45 2017 -0700 |
| committer | Catalin Marinas <catalin.marinas@arm.com> | Fri Apr 28 15:23:36 2017 +0100 |
| tree | 44a7b3559a6c24f2f7e4dbe731251b0b652e3131 | |
| parent | 24af6c4e4e0f6e9803bec8dca0f7748afbb2bbf0 [diff] |
arm64: pmu: Wire-up Cortex A53 L2 cache events and DTLB refills Add missing L2 cache events: read/write accesses and misses, as well as the DTLB refills. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>