| commit | ec1e12645ff3987f660ef9dc21c9db548b43ee9b | [log] [tgz] |
|---|---|---|
| author | José Roberto de Souza <jose.souza@intel.com> | Thu Feb 27 14:00:51 2020 -0800 |
| committer | José Roberto de Souza <jose.souza@intel.com> | Mon Mar 02 12:00:39 2020 -0800 |
| tree | b7adb6d88d2693d1e9702333610e1686d5333176 | |
| parent | ccc495fd7ac3815702378712bccc1cbfc7852b58 [diff] |
drm/i915/tgl: Implement Wa_1409804808 This workaround the CS not done issue on PIPE_CONTROL. v2: - replaced BIT() by REG_BIT() in all GEN7_ROW_CHICKEN2() bits - shortened the name of the new bit BSpec: 52890 BSpec: 46218 Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200227220101.321671-1-jose.souza@intel.com