| commit | e4e06a50b04296d17a4cf098a515fb452106ecf0 | [log] [tgz] |
|---|---|---|
| author | Lars Povlsen <lars.povlsen@microchip.com> | Mon Jun 15 15:32:41 2020 +0200 |
| committer | Arnd Bergmann <arnd@arndb.de> | Tue Jul 28 11:13:48 2020 +0200 |
| tree | f01c7437b53f639c36dd96aae49ef5b4783d6ba2 | |
| parent | 39c8378a1cdf856a3671b6431f99352b75a07248 [diff] |
arm64: dts: sparx5: Add Sparx5 SoC DPLL clock This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock to misc peripherals, specifically the SDHCI/eMMC controller. Link: https://lore.kernel.org/r/20200615133242.24911-10-lars.povlsen@microchip.com Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>