| commit | e01b1bfd88f9c5ec32b471a5a696a79f45740e63 | [log] [tgz] |
|---|---|---|
| author | Hai Li <hali@codeaurora.org> | Fri Sep 11 15:56:09 2015 -0400 |
| committer | Rob Clark <robdclark@gmail.com> | Thu Oct 22 15:39:54 2015 -0400 |
| tree | 0d86b5bf966f9e6d3a5ea9ea614c3bc6e6b7abec | |
| parent | 556a76e51b5c8e16986e2cc0a5e14306a4e2505a [diff] |
drm/msm/dsi: Updata LNn_CFG4 register settings for 28nm PHY The current settings for 28nm PHY data lane CFG4 registers do not work with certain panels. This change is to modify them to hw recommended values. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>