| commit | db9635cc14f316346c5b3954153d7e8c7016105d | [log] [tgz] |
|---|---|---|
| author | Alex Deucher <alexander.deucher@amd.com> | Mon Oct 10 12:05:32 2016 -0400 |
| committer | Alex Deucher <alexander.deucher@amd.com> | Tue Oct 25 14:38:32 2016 -0400 |
| tree | 2ee8ec2d421def4a79eaa1bad0d3e478ba9b49de | |
| parent | 34817db6c73d110d460daf02b977f583caa05a97 [diff] |
drm/amdgpu: used cached gca values for vi_read_register (v2) Using the cached values has less latency for bare metal and SR-IOV, and prevents reading back bogus values if the engine is powergated. v2: fix typo in tile idx calculation Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>