tree ca6103a3d1976832031e2c6561ce768432ce75ad
parent 398aa66827155ef52bab58bebd24597d90968929
author Linus Walleij <linus.walleij@stericsson.com> 1277276388 +0100
committer Russell King <rmk+kernel@arm.linux.org.uk> 1278683207 +0100

ARM: 6184/2: ux500: use neutral PRCMU base

The MTU wallclock timing fix-up patch was hardwired to the DB8500
causing a regression. This makes it work on the DB5500 as well.

Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>