| commit | fbd1cec57064aa1380726ec899c49fcd84e702b9 | [log] [tgz] |
|---|---|---|
| author | Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | Sat Dec 09 16:59:17 2017 +0300 |
| committer | Vineet Gupta <vgupta@synopsys.com> | Wed Dec 20 12:41:45 2017 -0800 |
| tree | 17a239d70f4f03ca2121d88f16d0c9c4941be511 | |
| parent | 7bde846d0957fb81ac0bf8c4e2cab284a1da34e0 [diff] |
ARC: [plat-axs103]: Set initial core pll output frequency Set initial core pll output frequency specified in device tree to 100MHz for SMP configuration and 90MHz for UP configuration. It will be applied at the core pll driver probing. Update platform quirk for decreasing core frequency for quad core configuration. Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>