tree 3773ba49525c135e13423ec5fc5df0bf80bbdd9f
parent b6da0ffb09ad4468e6749488909f04f1efac5de3
author Kevin Cernekee <cernekee@gmail.com> 1283832226 -0700
committer Ralf Baechle <ralf@linux-mips.org> 1311611213 +0100

MIPS: Add SYNC after cacheflush

On processors with deep write buffers, it is likely that many cycles
will pass between a CACHE instruction and the time the data actually
gets written out to DRAM.  Add a SYNC instruction to ensure that the
buffers get emptied before the flush functions return.

Actual problem seen in the wild:

1) dma_alloc_coherent() allocates cached memory

2) memset() is called to clear the new pages

3) dma_cache_wback_inv() is called to flush the zero data out to memory

4) dma_alloc_coherent() returns an uncached (kseg1) pointer to the
freshly allocated pages

5) Caller writes data through the kseg1 pointer

6) Buffered writeback data finally gets flushed out to DRAM

7) Part of caller's data is inexplicably zeroed out

This patch adds SYNC between steps 3 and 4, which fixed the problem.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>