| commit | 54ce17dd40fd846a7ac1e87e1103032933d2bd21 | [log] [tgz] |
|---|---|---|
| author | Biju Das <biju.das@bp.renesas.com> | Thu Sep 05 07:52:40 2019 +0100 |
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | Tue Oct 01 09:49:40 2019 +0200 |
| tree | a377e3a27addb28a179097c950c2ff047fc7841a | |
| parent | be67c41781cb4c06a4acb0b92db0cbb728e955e2 [diff] |
dt-bindings: clk: Add r8a774b1 CPG Core Clock Definitions
Add all RZ/G2N Clock Pulse Generator Core Clock Outputs, as listed in
Table 8.2d ("List of Clocks [RZ/G2N]") of the RZ/G2N Hardware User's
Manual.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Link: https://lore.kernel.org/r/1567666360-28035-1-git-send-email-biju.das@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>