| commit | ba0b3a977ecf525231d36f2d9f3a6ea05c35090a | [log] [tgz] |
|---|---|---|
| author | Curtis Malainey <cujomalainey@chromium.org> | Tue Nov 05 17:13:35 2019 -0800 |
| committer | Mark Brown <broonie@kernel.org> | Mon Nov 11 13:02:06 2019 +0000 |
| tree | 341e7425717c32d3e09685b9a54b07732efbb925 | |
| parent | 55229597a94531726878229ccfcd3fe4ec572dc3 [diff] |
ASoC: rt5677: Set ADC clock to use PLL and enable ASRC Use the PLL to kept the correct 24M clock rate so frequency shift does not occur when using the DSP VAD. Signed-off-by: Curtis Malainey <cujomalainey@chromium.org> Link: https://lore.kernel.org/r/20191106011335.223061-11-cujomalainey@chromium.org Signed-off-by: Mark Brown <broonie@kernel.org>