| commit | b02d4081a5260778ec9d20ac1f079c2b503d9943 | [log] [tgz] |
|---|---|---|
| author | Rex Zhu <Rex.Zhu@amd.com> | Fri Nov 11 11:18:07 2016 +0800 |
| committer | Alex Deucher <alexander.deucher@amd.com> | Wed Nov 23 15:08:39 2016 -0500 |
| tree | e218336ddad103867d827635c8f7b0bfee576a00 | |
| parent | 58a6a7dd19980087f5bbbcf7fcfc02a90b72de79 [diff] |
drm/amdgpu: refine cz uvd clock gate logic. sw clockgate was used on uvd6.0. when uvd is idle, we gate the uvd clock. when decode, we ungate the uvd clock. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>