e1000e: reformat comment blocks, cosmetic changes only
Adjusting the comment blocks here to be code-style compliant. no
code changes.
Changed some copyright dates to 2008.
Indentation fixes.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c
index 0ae3955..8440156 100644
--- a/drivers/net/e1000e/ich8lan.c
+++ b/drivers/net/e1000e/ich8lan.c
@@ -1,7 +1,7 @@
/*******************************************************************************
Intel PRO/1000 Linux driver
- Copyright(c) 1999 - 2007 Intel Corporation.
+ Copyright(c) 1999 - 2008 Intel Corporation.
This program is free software; you can redistribute it and/or modify it
under the terms and conditions of the GNU General Public License,
@@ -243,8 +243,7 @@
u32 sector_end_addr;
u16 i;
- /* Can't read flash registers if the register set isn't mapped.
- */
+ /* Can't read flash registers if the register set isn't mapped. */
if (!hw->flash_address) {
hw_dbg(hw, "ERROR: Flash registers not mapped\n");
return -E1000_ERR_CONFIG;
@@ -254,17 +253,21 @@
gfpreg = er32flash(ICH_FLASH_GFPREG);
- /* sector_X_addr is a "sector"-aligned address (4096 bytes)
+ /*
+ * sector_X_addr is a "sector"-aligned address (4096 bytes)
* Add 1 to sector_end_addr since this sector is included in
- * the overall size. */
+ * the overall size.
+ */
sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
/* flash_base_addr is byte-aligned */
nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
- /* find total size of the NVM, then cut in half since the total
- * size represents two separate NVM banks. */
+ /*
+ * find total size of the NVM, then cut in half since the total
+ * size represents two separate NVM banks.
+ */
nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
<< FLASH_SECTOR_ADDR_SHIFT;
nvm->flash_bank_size /= 2;
@@ -496,7 +499,8 @@
if (ret_val)
return ret_val;
- /* Initialize the PHY from the NVM on ICH platforms. This
+ /*
+ * Initialize the PHY from the NVM on ICH platforms. This
* is needed due to an issue where the NVM configuration is
* not properly autoloaded after power transitions.
* Therefore, after each PHY reset, we will load the
@@ -523,7 +527,8 @@
udelay(100);
} while ((!data) && --loop);
- /* If basic configuration is incomplete before the above loop
+ /*
+ * If basic configuration is incomplete before the above loop
* count reaches 0, loading the configuration from NVM will
* leave the PHY in a bad state possibly resulting in no link.
*/
@@ -536,8 +541,10 @@
data &= ~E1000_STATUS_LAN_INIT_DONE;
ew32(STATUS, data);
- /* Make sure HW does not configure LCD from PHY
- * extended configuration before SW configuration */
+ /*
+ * Make sure HW does not configure LCD from PHY
+ * extended configuration before SW configuration
+ */
data = er32(EXTCNF_CTRL);
if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
return 0;
@@ -551,8 +558,7 @@
cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
- /* Configure LCD from extended configuration
- * region. */
+ /* Configure LCD from extended configuration region. */
/* cnf_base_addr is in DWORD */
word_addr = (u16)(cnf_base_addr << 1);
@@ -681,8 +687,8 @@
s32 ret_val;
u16 phy_data, offset, mask;
- /* Polarity is determined based on the reversal feature
- * being enabled.
+ /*
+ * Polarity is determined based on the reversal feature being enabled.
*/
if (phy->polarity_correction) {
offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
@@ -731,8 +737,10 @@
phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
ew32(PHY_CTRL, phy_ctrl);
- /* Call gig speed drop workaround on LPLU before accessing
- * any PHY registers */
+ /*
+ * Call gig speed drop workaround on LPLU before accessing
+ * any PHY registers
+ */
if ((hw->mac.type == e1000_ich8lan) &&
(hw->phy.type == e1000_phy_igp_3))
e1000e_gig_downshift_workaround_ich8lan(hw);
@@ -747,30 +755,32 @@
phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
ew32(PHY_CTRL, phy_ctrl);
- /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
+ /*
+ * LPLU and SmartSpeed are mutually exclusive. LPLU is used
* during Dx states where the power conservation is most
* important. During driver activity we should enable
- * SmartSpeed, so performance is maintained. */
+ * SmartSpeed, so performance is maintained.
+ */
if (phy->smart_speed == e1000_smart_speed_on) {
ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
- &data);
+ &data);
if (ret_val)
return ret_val;
data |= IGP01E1000_PSCFR_SMART_SPEED;
ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
- data);
+ data);
if (ret_val)
return ret_val;
} else if (phy->smart_speed == e1000_smart_speed_off) {
ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
- &data);
+ &data);
if (ret_val)
return ret_val;
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
- data);
+ data);
if (ret_val)
return ret_val;
}
@@ -804,34 +814,32 @@
if (!active) {
phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
ew32(PHY_CTRL, phy_ctrl);
- /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
+ /*
+ * LPLU and SmartSpeed are mutually exclusive. LPLU is used
* during Dx states where the power conservation is most
* important. During driver activity we should enable
- * SmartSpeed, so performance is maintained. */
+ * SmartSpeed, so performance is maintained.
+ */
if (phy->smart_speed == e1000_smart_speed_on) {
- ret_val = e1e_rphy(hw,
- IGP01E1000_PHY_PORT_CONFIG,
- &data);
+ ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
+ &data);
if (ret_val)
return ret_val;
data |= IGP01E1000_PSCFR_SMART_SPEED;
- ret_val = e1e_wphy(hw,
- IGP01E1000_PHY_PORT_CONFIG,
- data);
+ ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
+ data);
if (ret_val)
return ret_val;
} else if (phy->smart_speed == e1000_smart_speed_off) {
- ret_val = e1e_rphy(hw,
- IGP01E1000_PHY_PORT_CONFIG,
- &data);
+ ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
+ &data);
if (ret_val)
return ret_val;
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
- ret_val = e1e_wphy(hw,
- IGP01E1000_PHY_PORT_CONFIG,
- data);
+ ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
+ data);
if (ret_val)
return ret_val;
}
@@ -841,23 +849,21 @@
phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
ew32(PHY_CTRL, phy_ctrl);
- /* Call gig speed drop workaround on LPLU before accessing
- * any PHY registers */
+ /*
+ * Call gig speed drop workaround on LPLU before accessing
+ * any PHY registers
+ */
if ((hw->mac.type == e1000_ich8lan) &&
(hw->phy.type == e1000_phy_igp_3))
e1000e_gig_downshift_workaround_ich8lan(hw);
/* When LPLU is enabled, we should disable SmartSpeed */
- ret_val = e1e_rphy(hw,
- IGP01E1000_PHY_PORT_CONFIG,
- &data);
+ ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
if (ret_val)
return ret_val;
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
- ret_val = e1e_wphy(hw,
- IGP01E1000_PHY_PORT_CONFIG,
- data);
+ ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
}
return 0;
@@ -944,7 +950,8 @@
ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
- /* Either we should have a hardware SPI cycle in progress
+ /*
+ * Either we should have a hardware SPI cycle in progress
* bit to check against, in order to start a new cycle or
* FDONE bit should be changed in the hardware so that it
* is 1 after hardware reset, which can then be used as an
@@ -953,15 +960,19 @@
*/
if (hsfsts.hsf_status.flcinprog == 0) {
- /* There is no cycle running at present,
- * so we can start a cycle */
- /* Begin by setting Flash Cycle Done. */
+ /*
+ * There is no cycle running at present,
+ * so we can start a cycle
+ * Begin by setting Flash Cycle Done.
+ */
hsfsts.hsf_status.flcdone = 1;
ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
ret_val = 0;
} else {
- /* otherwise poll for sometime so the current
- * cycle has a chance to end before giving up. */
+ /*
+ * otherwise poll for sometime so the current
+ * cycle has a chance to end before giving up.
+ */
for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
if (hsfsts.hsf_status.flcinprog == 0) {
@@ -971,8 +982,10 @@
udelay(1);
}
if (ret_val == 0) {
- /* Successful in waiting for previous cycle to timeout,
- * now set the Flash Cycle Done. */
+ /*
+ * Successful in waiting for previous cycle to timeout,
+ * now set the Flash Cycle Done.
+ */
hsfsts.hsf_status.flcdone = 1;
ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
} else {
@@ -1077,10 +1090,12 @@
ret_val = e1000_flash_cycle_ich8lan(hw,
ICH_FLASH_READ_COMMAND_TIMEOUT);
- /* Check if FCERR is set to 1, if set to 1, clear it
+ /*
+ * Check if FCERR is set to 1, if set to 1, clear it
* and try the whole sequence a few more times, else
* read in (shift in) the Flash Data0, the order is
- * least significant byte first msb to lsb */
+ * least significant byte first msb to lsb
+ */
if (ret_val == 0) {
flash_data = er32flash(ICH_FLASH_FDATA0);
if (size == 1) {
@@ -1090,7 +1105,8 @@
}
break;
} else {
- /* If we've gotten here, then things are probably
+ /*
+ * If we've gotten here, then things are probably
* completely hosed, but if the error condition is
* detected, it won't hurt to give it another try...
* ICH_FLASH_CYCLE_REPEAT_COUNT times.
@@ -1168,18 +1184,20 @@
ret_val = e1000e_update_nvm_checksum_generic(hw);
if (ret_val)
- return ret_val;;
+ return ret_val;
if (nvm->type != e1000_nvm_flash_sw)
- return ret_val;;
+ return ret_val;
ret_val = e1000_acquire_swflag_ich8lan(hw);
if (ret_val)
- return ret_val;;
+ return ret_val;
- /* We're writing to the opposite bank so if we're on bank 1,
+ /*
+ * We're writing to the opposite bank so if we're on bank 1,
* write to bank 0 etc. We also need to erase the segment that
- * is going to be written */
+ * is going to be written
+ */
if (!(er32(EECD) & E1000_EECD_SEC1VAL)) {
new_bank_offset = nvm->flash_bank_size;
old_bank_offset = 0;
@@ -1191,9 +1209,11 @@
}
for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
- /* Determine whether to write the value stored
+ /*
+ * Determine whether to write the value stored
* in the other NVM bank or a modified value stored
- * in the shadow RAM */
+ * in the shadow RAM
+ */
if (dev_spec->shadow_ram[i].modified) {
data = dev_spec->shadow_ram[i].value;
} else {
@@ -1202,12 +1222,14 @@
&data);
}
- /* If the word is 0x13, then make sure the signature bits
+ /*
+ * If the word is 0x13, then make sure the signature bits
* (15:14) are 11b until the commit has completed.
* This will allow us to write 10b which indicates the
* signature is valid. We want to do this after the write
* has completed so that we don't mark the segment valid
- * while the write is still in progress */
+ * while the write is still in progress
+ */
if (i == E1000_ICH_NVM_SIG_WORD)
data |= E1000_ICH_NVM_SIG_MASK;
@@ -1230,18 +1252,22 @@
break;
}
- /* Don't bother writing the segment valid bits if sector
- * programming failed. */
+ /*
+ * Don't bother writing the segment valid bits if sector
+ * programming failed.
+ */
if (ret_val) {
hw_dbg(hw, "Flash commit failed.\n");
e1000_release_swflag_ich8lan(hw);
return ret_val;
}
- /* Finally validate the new segment by setting bit 15:14
+ /*
+ * Finally validate the new segment by setting bit 15:14
* to 10b in word 0x13 , this can be done without an
* erase as well since these bits are 11 to start with
- * and we need to change bit 14 to 0b */
+ * and we need to change bit 14 to 0b
+ */
act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
e1000_read_flash_word_ich8lan(hw, act_offset, &data);
data &= 0xBFFF;
@@ -1253,10 +1279,12 @@
return ret_val;
}
- /* And invalidate the previously valid segment by setting
+ /*
+ * And invalidate the previously valid segment by setting
* its signature word (0x13) high_byte to 0b. This can be
* done without an erase because flash erase sets all bits
- * to 1's. We can write 1's to 0's without an erase */
+ * to 1's. We can write 1's to 0's without an erase
+ */
act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
if (ret_val) {
@@ -1272,7 +1300,8 @@
e1000_release_swflag_ich8lan(hw);
- /* Reload the EEPROM, or else modifications will not appear
+ /*
+ * Reload the EEPROM, or else modifications will not appear
* until after the next adapter reset.
*/
e1000e_reload_nvm(hw);
@@ -1294,7 +1323,8 @@
s32 ret_val;
u16 data;
- /* Read 0x19 and check bit 6. If this bit is 0, the checksum
+ /*
+ * Read 0x19 and check bit 6. If this bit is 0, the checksum
* needs to be fixed. This bit is an indication that the NVM
* was prepared by OEM software and did not calculate the
* checksum...a likely scenario.
@@ -1364,14 +1394,17 @@
ew32flash(ICH_FLASH_FDATA0, flash_data);
- /* check if FCERR is set to 1 , if set to 1, clear it
- * and try the whole sequence a few more times else done */
+ /*
+ * check if FCERR is set to 1 , if set to 1, clear it
+ * and try the whole sequence a few more times else done
+ */
ret_val = e1000_flash_cycle_ich8lan(hw,
ICH_FLASH_WRITE_COMMAND_TIMEOUT);
if (!ret_val)
break;
- /* If we're here, then things are most likely
+ /*
+ * If we're here, then things are most likely
* completely hosed, but if the error condition
* is detected, it won't hurt to give it another
* try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
@@ -1462,9 +1495,10 @@
hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
- /* Determine HW Sector size: Read BERASE bits of hw flash status
- * register */
- /* 00: The Hw sector is 256 bytes, hence we need to erase 16
+ /*
+ * Determine HW Sector size: Read BERASE bits of hw flash status
+ * register
+ * 00: The Hw sector is 256 bytes, hence we need to erase 16
* consecutive sectors. The start index for the nth Hw sector
* can be calculated as = bank * 4096 + n * 256
* 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
@@ -1511,13 +1545,16 @@
if (ret_val)
return ret_val;
- /* Write a value 11 (block Erase) in Flash
- * Cycle field in hw flash control */
+ /*
+ * Write a value 11 (block Erase) in Flash
+ * Cycle field in hw flash control
+ */
hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
- /* Write the last 24 bits of an index within the
+ /*
+ * Write the last 24 bits of an index within the
* block into Flash Linear address field in Flash
* Address.
*/
@@ -1529,13 +1566,14 @@
if (ret_val == 0)
break;
- /* Check if FCERR is set to 1. If 1,
+ /*
+ * Check if FCERR is set to 1. If 1,
* clear it and try the whole sequence
- * a few more times else Done */
+ * a few more times else Done
+ */
hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
if (hsfsts.hsf_status.flcerr == 1)
- /* repeat for some time before
- * giving up */
+ /* repeat for some time before giving up */
continue;
else if (hsfsts.hsf_status.flcdone == 0)
return ret_val;
@@ -1585,7 +1623,8 @@
ret_val = e1000e_get_bus_info_pcie(hw);
- /* ICH devices are "PCI Express"-ish. They have
+ /*
+ * ICH devices are "PCI Express"-ish. They have
* a configuration space, but do not contain
* PCI Express Capability registers, so bus width
* must be hardcoded.
@@ -1608,7 +1647,8 @@
u32 ctrl, icr, kab;
s32 ret_val;
- /* Prevent the PCI-E bus from sticking if there is no TLP connection
+ /*
+ * Prevent the PCI-E bus from sticking if there is no TLP connection
* on the last TLP read/write transaction when MAC is reset.
*/
ret_val = e1000e_disable_pcie_master(hw);
@@ -1619,7 +1659,8 @@
hw_dbg(hw, "Masking off all interrupts\n");
ew32(IMC, 0xffffffff);
- /* Disable the Transmit and Receive units. Then delay to allow
+ /*
+ * Disable the Transmit and Receive units. Then delay to allow
* any pending transactions to complete before we hit the MAC
* with the global reset.
*/
@@ -1640,7 +1681,8 @@
ctrl = er32(CTRL);
if (!e1000_check_reset_block(hw)) {
- /* PHY HW reset requires MAC CORE reset at the same
+ /*
+ * PHY HW reset requires MAC CORE reset at the same
* time to make sure the interface between MAC and the
* external PHY is reset.
*/
@@ -1724,8 +1766,10 @@
E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
ew32(TXDCTL1, txdctl);
- /* ICH8 has opposite polarity of no_snoop bits.
- * By default, we should use snoop behavior. */
+ /*
+ * ICH8 has opposite polarity of no_snoop bits.
+ * By default, we should use snoop behavior.
+ */
if (mac->type == e1000_ich8lan)
snoop = PCIE_ICH8_SNOOP_ALL;
else
@@ -1736,7 +1780,8 @@
ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
ew32(CTRL_EXT, ctrl_ext);
- /* Clear all of the statistics registers (clear on read). It is
+ /*
+ * Clear all of the statistics registers (clear on read). It is
* important that we do this after we have tried to establish link
* because the symbol error count will increment wildly if there
* is no link.
@@ -1813,7 +1858,8 @@
if (e1000_check_reset_block(hw))
return 0;
- /* ICH parts do not have a word in the NVM to determine
+ /*
+ * ICH parts do not have a word in the NVM to determine
* the default flow control setting, so we explicitly
* set it to full.
*/
@@ -1853,9 +1899,11 @@
ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
ew32(CTRL, ctrl);
- /* Set the mac to wait the maximum time between each iteration
+ /*
+ * Set the mac to wait the maximum time between each iteration
* and increase the max iterations when polling the phy;
- * this fixes erroneous timeouts at 10Mbps. */
+ * this fixes erroneous timeouts at 10Mbps.
+ */
ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
if (ret_val)
return ret_val;
@@ -1882,7 +1930,7 @@
* @speed: pointer to store current link speed
* @duplex: pointer to store the current link duplex
*
- * Calls the generic get_speed_and_duplex to retreive the current link
+ * Calls the generic get_speed_and_duplex to retrieve the current link
* information and then calls the Kumeran lock loss workaround for links at
* gigabit speeds.
**/
@@ -1930,9 +1978,11 @@
if (!dev_spec->kmrn_lock_loss_workaround_enabled)
return 0;
- /* Make sure link is up before proceeding. If not just return.
+ /*
+ * Make sure link is up before proceeding. If not just return.
* Attempting this while link is negotiating fouled up link
- * stability */
+ * stability
+ */
ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
if (!link)
return 0;
@@ -1961,8 +2011,10 @@
E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
ew32(PHY_CTRL, phy_ctrl);
- /* Call gig speed drop workaround on Gig disable before accessing
- * any PHY registers */
+ /*
+ * Call gig speed drop workaround on Gig disable before accessing
+ * any PHY registers
+ */
e1000e_gig_downshift_workaround_ich8lan(hw);
/* unable to acquire PCS lock */
@@ -1970,7 +2022,7 @@
}
/**
- * e1000_set_kmrn_lock_loss_workaound_ich8lan - Set Kumeran workaround state
+ * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
* @hw: pointer to the HW structure
* @state: boolean value used to set the current Kumeran workaround state
*
@@ -2017,8 +2069,10 @@
E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
ew32(PHY_CTRL, reg);
- /* Call gig speed drop workaround on Gig disable before
- * accessing any PHY registers */
+ /*
+ * Call gig speed drop workaround on Gig disable before
+ * accessing any PHY registers
+ */
if (hw->mac.type == e1000_ich8lan)
e1000e_gig_downshift_workaround_ich8lan(hw);