| commit | aa4747c00a2dd034c5fdf70ca73b1674ca15beb3 | [log] [tgz] |
|---|---|---|
| author | Rex Zhu <Rex.Zhu@amd.com> | Fri Nov 04 20:35:46 2016 +0800 |
| committer | Alex Deucher <alexander.deucher@amd.com> | Fri Nov 11 10:21:04 2016 -0500 |
| tree | 9e3cc3ab768fc3c1955c5090a06ac2fd26208564 | |
| parent | dc2f8a9aa98c5983d5faacf7e9843f8d15b5da9c [diff] |
drm/amdgpu: refine uvd_4.2 clock gate sequence. 1. partial revert commit 91db308d6e96. not set uvd bypass mode. 2. enable uvd cg before initialize uvd. 3. set uvd clock to default value 100MHz. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>