| commit | a3a80544acb3dfa97d43b8eee1332fe1fca7fe51 | [log] [tgz] |
|---|---|---|
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | Tue Aug 05 10:25:55 2014 +0100 |
| committer | Will Deacon <will.deacon@arm.com> | Mon Aug 18 19:47:03 2014 +0100 |
| tree | 3ca111e74a6addb43b403bd43cfb73bc0b3aab13 | |
| parent | 7d1311b93e58ed55f3a31cc8f94c4b8fe988a2b9 [diff] |
arm64: fix typo in I-cache policy detection This removes an unfortunately placed semi-colon resulting in all instruction caches being classified as AIVIVT. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>