| commit | 39e08affecf0998be1b01f4752016e33fa98eb9a | [log] [tgz] |
|---|---|---|
| author | Thierry Reding <treding@nvidia.com> | Wed Aug 30 17:38:39 2017 +0200 |
| committer | Thierry Reding <treding@nvidia.com> | Fri Oct 20 14:19:54 2017 +0200 |
| tree | 6dcbc100ab55cb4ddc6c70a05cab59aa7c934a77 | |
| parent | a4bfa0961c4bccbfd5f23d1283fa3d40e6af1b59 [diff] |
drm/tegra: dc: Make sure to set the module clock rate When applying the PLL changes from the computed state object, make sure to set the rate of the display controller module clock. Failing to do so can yield to a situation where the parent will be set to the proper pixel clock, but the module clock will be divided down to the rate that is happened to be set to before the parent rate change. Signed-off-by: Thierry Reding <treding@nvidia.com>