| commit | a08c832f277d7a6f9d3b341a5d5df2f5576220d8 | [log] [tgz] |
|---|---|---|
| author | Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | Sat Dec 09 16:59:15 2017 +0300 |
| committer | Vineet Gupta <vgupta@synopsys.com> | Wed Dec 20 12:41:44 2017 -0800 |
| tree | 904c7baed42e96d959eaaa26c943abf4b95ee0c8 | |
| parent | c18fc9071762769acb4040cabae45c817aefc537 [diff] |
ARC: [plat-hsdk]: Set initial core pll output frequency Set initial core pll output frequency specified in device tree to 1GHz. It will be applied at the core pll driver probing. Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>