| commit | 9f2efa320d395050abd0f39842843bb460736515 | [log] [tgz] |
|---|---|---|
| author | Marc Zyngier <marc.zyngier@arm.com> | Sun Dec 03 17:47:03 2017 +0000 |
| committer | Marc Zyngier <marc.zyngier@arm.com> | Mon Mar 19 13:05:10 2018 +0000 |
| tree | 769cc9c3900c0a8ae5d8f49172bd6d9d06f86ade | |
| parent | e3f019b37b580c3b954419212da26ac5db412a08 [diff] |
arm64; insn: Add encoder for the EXTR instruction Add an encoder for the EXTR instruction, which also implements the ROR variant (where Rn == Rm). Acked-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>