tree b7a20aa263665d84e1322c4bb38972896adf93b2
parent 6a68735a9d1fc8b10828f6775a363170f02a862b
author Ville Syrjälä <ville.syrjala@linux.intel.com> 1393503792 +0200
committer Daniel Vetter <daniel.vetter@ffwll.ch> 1394051431 +0100

drm/i915: Fix DDI port_clock for VGA output

On DDI there's no PLL as such to generate the pixel clock for VGA.
Instead we derive the pixel clock from the FDI link frequency. So
to make .compute_config match what .get_config does, we need to
set the port_clock based on the FDI link frequency.

Note that we don't even check the port_clock when selecting the
PLL for VGA output. We just assume SPLL at 1.35GHz is what we want,
and that does match with the asumption of FDI frequency of 2.7Ghz
we have in intel_fdi_link_freq().

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74955
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>