| commit | 8e27a2d4cd76095c80dbbf63548175659d4b9d76 | [log] [tgz] |
|---|---|---|
| author | Ilya Bakoulin <Ilya.Bakoulin@amd.com> | Thu Mar 28 14:43:29 2019 -0400 |
| committer | Alex Deucher <alexander.deucher@amd.com> | Sat Jun 22 09:34:09 2019 -0500 |
| tree | d7ef5c0d536ba6ed87877d95775da7cdda2147dd | |
| parent | 0213541d4b6b241a83611dd8324af024f87b5368 [diff] |
drm/amd/display: Fix DCFCLK and SOCCLK not set [Why] If voltage level > 0, DCFCLK and SOCCLK could be 0 during DML calculations, which ended up causing an assert. [How] Initialize dcfclk_mhz and socclk_mhz values according to the voltage level. Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>