| commit | 83f6941a42a5e773a5e850944a0f1200841eae65 | [log] [tgz] |
|---|---|---|
| author | Takeshi Kihara <takeshi.kihara.df@renesas.com> | Fri May 11 12:22:24 2018 +0900 |
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | Wed May 23 14:43:32 2018 +0200 |
| tree | 1a46cec7573e90e0431444169db50ed14c2382dc | |
| parent | 6d4036a1e3b3ac0f3eebda5a0bbc6d78ebc14389 [diff] |
pinctrl: sh-pfc: r8a77990: Add bias pinconf support This patch implements control of pull-up and pull-down. On this SoC there is no simple mapping of GP pins to bias register bits, so we need a table. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>