| commit | 809a6a62b6b3e688e6b4d57acf296d6f25620c8a | [log] [tgz] |
|---|---|---|
| author | Rex Zhu <Rex.Zhu@amd.com> | Tue Nov 08 20:43:50 2016 +0800 |
| committer | Alex Deucher <alexander.deucher@amd.com> | Fri Nov 11 10:21:11 2016 -0500 |
| tree | 67f7c50e2c4fa52c46ed2c30e58b2b36ebf60c79 | |
| parent | 68260f340e191a67056b6c27f958f09029b9e11f [diff] |
drm/amdgpu: refine uvd 5.0 clock gate feature. 1. fix uvd cg status not correct. 2. fix uvd pg can't work on tonga. 3. enable uvd mgcg. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tom St Denis <tom.stdenis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>