| commit | e1236bc06c534a97f73e09aed5e1094108553e9f | [log] [tgz] |
|---|---|---|
| author | Changbin Du <changbin.du@intel.com> | Thu Apr 06 10:55:02 2017 +0800 |
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | Wed Apr 12 13:57:42 2017 +0800 |
| tree | 16faf6807220b91820833a47fcc9818a93a46801 | |
| parent | 0b063bd3ea9c13df78c82aa742e581c39f9d6156 [diff] |
drm/i915/gvt: Align render mmio list to cacheline Make the global mmio list be cacheline aligned to improve performance. Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>