| commit | 7fe538a4d64135d8f8e4aca8d0aedf266958025c | [log] [tgz] |
|---|---|---|
| author | Charlene Liu <charlene.liu@amd.com> | Fri Mar 01 11:12:50 2019 -0500 |
| committer | Alex Deucher <alexander.deucher@amd.com> | Wed Mar 20 23:39:48 2019 -0500 |
| tree | 4acc1d7a90038a20cf4b823e7e5d5b5fe2b8927d | |
| parent | ae5041f3a03134a4cd5fc1c41e082c0e5d290392 [diff] |
drm/amd/display: fix DP 422 VID_M half the rate issue. [Description] when programming VID_TIMING, we were using the original VESA timing for DP_VIDM/N. for YCbCr420 or compressed YCbCr422, using half rate as YCbCr444. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>