| commit | 7d708ee40a6b9ca1112a322e554c887df105b025 | [log] [tgz] |
|---|---|---|
| author | Imre Deak <imre.deak@intel.com> | Wed Apr 17 14:04:50 2013 +0300 |
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | Fri May 10 21:56:35 2013 +0200 |
| tree | ce5a29a139c6e6c1c0c2d3e156ba3f8f48800baf | |
| parent | bc5ead8c09b51e85d110132495a9bfa58dc39dab [diff] |
drm/i915: HSW: allow PCH clock gating for suspend For the device to enter D3 we should enable PCH clock gating. v2: - use HAS_PCH_LPT instead of IS_HASWELL (Ville, Paolo) - rename lpt_allow_clock_gating to lpt_suspend_hw (Paolo) Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>