| commit | 960e9836f7217c682ef6cf4038c7271ab401cc7d | [log] [tgz] |
|---|---|---|
| author | Vandita Kulkarni <vandita.kulkarni@intel.com> | Tue Jul 30 13:06:44 2019 +0530 |
| committer | Uma Shankar <uma.shankar@intel.com> | Thu Aug 08 18:37:50 2019 +0530 |
| tree | 28f137ad7831543a8f462fd042bf3cb73f3ecb6d | |
| parent | 3522a33a2746b519b27a675639ac976c9189d1de [diff] |
drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl Latency programming remains same as that of ICL and setting latency otimization for PCS_DW1 lanes is same as that of EHL, hence extending it to TGL. Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190730073648.5157-3-vandita.kulkarni@intel.com