| commit | 2464bc7c2897b7549146a743045089d3aea7b85b | [log] [tgz] |
|---|---|---|
| author | Horatiu Vultur <horatiu.vultur@microchip.com> | Tue Jun 23 11:05:40 2020 +0200 |
| committer | David S. Miller <davem@davemloft.net> | Tue Jun 23 14:38:05 2020 -0700 |
| tree | b6aa045cdd1f7c5fd325ba1d054330040fe96f90 | |
| parent | 26ac10be3c80a26d03c950b7387c4b9566c260b6 [diff] |
bridge: uapi: mrp: Fix MRP_PORT_ROLE
Currently the MRP_PORT_ROLE_NONE has the value 0x2 but this is in conflict
with the IEC 62439-2 standard. The standard defines the following port
roles: primary (0x0), secondary(0x1), interconnect(0x2).
Therefore remove the port role none.
Fixes: 4714d13791f831 ("bridge: uapi: mrp: Add mrp attributes.")
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>