| commit | 2d0b10fc5111bb4a902e9be378496d04c401ab81 | [log] [tgz] |
|---|---|---|
| author | Abhinav Kumar <abhinavk@codeaurora.org> | Thu Jun 07 13:50:29 2018 -0700 |
| committer | Sean Paul <seanpaul@chromium.org> | Thu Jul 26 10:40:15 2018 -0400 |
| tree | 252ad33176f951e4297d60e8107ffc79e093ef96 | |
| parent | bb676df12b5e81cab57d1a212a6e9cfc343875a7 [diff] |
drm/msm: higher values of pclk can exceed 32 bits when multiplied by a factor Make the pclk_rate u64 to accommodate higher pixel clock rates. Changes in v3: - Converted pclk_rate to u32 (Archit) - Rebase on dsi cleanup set in msm-next Cc: Sibi Sankar <sibis@codeaurora.org> Cc: Archit Taneja <architt@codeaurora.org> Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>