| commit | 73b1917454b3639ac1926c869f51e0dc20a0d22f | [log] [tgz] |
|---|---|---|
| author | Rex Zhu <rex.zhu@amd.com> | Thu Jul 05 16:34:13 2018 +0800 |
| committer | Alex Deucher <alexander.deucher@amd.com> | Tue Jul 10 14:16:39 2018 -0500 |
| tree | f17d07fe289e897ad5245eb6a80252841cb3803c | |
| parent | 02374bbd3bfa38cc6922fe56736716308c48f538 [diff] |
drm/amdgpu: Add CLK IP base offset so we can read/write the registers in CLK domain through RREG32/WREG32_SOC15 Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>