tree 4b2537d200a51e13ea9e2b439c58411f7769f325
parent bfca94590bfd3dcd958c542d2fb6406518150fee
author Russell King <rmk@dyn-67.arm.linux.org.uk> 1130940695 +0000
committer Russell King <rmk+kernel@arm.linux.org.uk> 1130940695 +0000

[ARM] Fix mm initialisation with write buffered write allocate caches

It seems that without the extra tlb flush, we may end up faulting
during the early kernel initialisation because the TLB can't see
the updated page tables.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>