| commit | 6b5b5fea3b767a269c303166fc41eba3dbc1154d | [log] [tgz] |
|---|---|---|
| author | Feifei Xu <Feifei.Xu@amd.com> | Mon Nov 27 17:32:44 2017 +0800 |
| committer | Alex Deucher <alexander.deucher@amd.com> | Wed Dec 06 12:48:26 2017 -0500 |
| tree | 2f807cb0e1552ea440b7f25ff8b352c19af659b2 | |
| parent | 51199920a288b7a75eb1edf00c6b4834ec64b6ca [diff] |
drm/amd/include:cleanup raven1 thm header files. Cleanup asic_reg/raven1/THM folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_default.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_default.h rename to drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_default.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_offset.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_offset.h rename to drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_offset.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_sh_mask.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_sh_mask.h rename to drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_sh_mask.h
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h index 5fb38f6..ae59a3f 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h
@@ -33,9 +33,9 @@ #include "asic_reg/nbio/nbio_7_0_offset.h" #include "asic_reg/nbio/nbio_7_0_sh_mask.h" -#include "asic_reg/raven1/THM/thm_10_0_default.h" -#include "asic_reg/raven1/THM/thm_10_0_offset.h" -#include "asic_reg/raven1/THM/thm_10_0_sh_mask.h" +#include "asic_reg/thm/thm_10_0_default.h" +#include "asic_reg/thm/thm_10_0_offset.h" +#include "asic_reg/thm/thm_10_0_sh_mask.h" #define ixDDI_PHY_GEN_STATUS 0x3FCE8