| commit | 649abf2f5d328a5a19824f712987f0a1de095332 | [log] [tgz] |
|---|---|---|
| author | Maxime Ripard <maxime@cerno.tech> | Thu Sep 03 10:00:47 2020 +0200 |
| committer | Maxime Ripard <maxime@cerno.tech> | Mon Sep 07 18:02:57 2020 +0200 |
| tree | 753de0b8a9275588a907c380817ad2d5d20a34f3 | |
| parent | 87ebcd42fb7b8d1d3269007a621e41ae96a0077e [diff] |
drm/vc4: crtc: Add FIFO depth to vc4_crtc_data Not all pixelvalve FIFOs in vc5 have the same depth, so we need to add that to our vc4_crtc_data structure to be able to compute the fill level properly later on. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Tested-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Link: https://patchwork.freedesktop.org/patch/msgid/7df3549c1bea9b0a27c784dc416bb9a831e4e18f.1599120059.git-series.maxime@cerno.tech