drm/i915: mask the video DIP frequency when changing it
Better safe than sorry. Currently we never change the frequency and
use the same for every infoframe type, so the only way to reproduce a
bug would be with the BIOS doing something.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 71e7af9..ce6e64d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1711,6 +1711,7 @@
#define VIDEO_DIP_FREQ_ONCE (0 << 16)
#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
+#define VIDEO_DIP_FREQ_MASK (3 << 16)
/* Panel power sequencing */
#define PP_STATUS 0x61200
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 6c96bb5..4a4ee8b 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -164,6 +164,7 @@
}
val |= intel_infoframe_enable(frame);
+ val &= ~VIDEO_DIP_FREQ_MASK;
val |= intel_infoframe_frequency(frame);
I915_WRITE(VIDEO_DIP_CTL, val);
@@ -203,6 +204,7 @@
}
val |= intel_infoframe_enable(frame);
+ val &= ~VIDEO_DIP_FREQ_MASK;
val |= intel_infoframe_frequency(frame);
I915_WRITE(reg, val);
@@ -236,6 +238,7 @@
}
val |= intel_infoframe_enable(frame);
+ val &= ~VIDEO_DIP_FREQ_MASK;
val |= intel_infoframe_frequency(frame);
I915_WRITE(reg, val);