| commit | 60afed72f51c7445aa06dc953b05f5672b607860 | [log] [tgz] |
|---|---|---|
| author | Tomer Tayar <Tomer.Tayar@cavium.com> | Thu Apr 06 15:58:30 2017 +0300 |
| committer | David S. Miller <davem@davemloft.net> | Thu Apr 06 14:26:31 2017 -0700 |
| tree | 01739ed7b696f08f2d03d388030516b1e55e22ed | |
| parent | 1558296251207bb0def2ae7cc045f8159ee0c204 [diff] |
qed: Configure cacheline size in HW Default HW configuration is optimal for an architecture where cache line size is 64B. During chip initialization, properly initialize the cache line size in HW to avoid possible redundant PCI transactions. Signed-off-by: Tomer Tayar <Tomer.Tayar@cavium.com> Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>