5d571068f71ebf41f434fa3f9b4ebcc9849d5efe - SHIFTPHONES/kernel/common

commit	5d571068f71ebf41f434fa3f9b4ebcc9849d5efe	[log] [tgz]
author	José Roberto de Souza <jose.souza@intel.com>	Thu Jul 25 17:24:10 2019 -0700
committer	Lucas De Marchi <lucas.demarchi@intel.com>	Thu Aug 01 14:36:54 2019 -0700
tree	cbbec55bcde1b7a40da466283d57c04b254d3da9
parent	01158da721c5fd5f321cfd7e3e955fbd83ba3124 [diff]

drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers

Tiger Lake has a new register offset for DC5 and DC6 residency counters.

v2:
  - Rename registers since they are not in the CSR memory range
    (requested by Anshuman)
  - Fix type (requested by Matthew)

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190726002412.5827-2-lucas.demarchi@intel.com

drivers/gpu/drm/i915/i915_debugfs.c[diff]
drivers/gpu/drm/i915/i915_reg.h[diff]

2 files changed

tree: cbbec55bcde1b7a40da466283d57c04b254d3da9