| commit | e67131d9b861eb753b077961e291fc21a59daa28 | [log] [tgz] |
|---|---|---|
| author | Petr Machata <petrm@mellanox.com> | Fri Jul 27 15:26:59 2018 +0300 |
| committer | David S. Miller <davem@davemloft.net> | Fri Jul 27 13:17:50 2018 -0700 |
| tree | 0560c7131bb24b1a202df3d36d41e85e28a30da2 | |
| parent | 746da42a1f60728fc0f3ba7818ffe8d1aa69cacd [diff] |
mlxsw: reg: Add QoS ReWrite Enable Register This register configures the rewrite enable (whether PCP or DSCP value in packet should be updated according to packet priority) per receive port. Signed-off-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>