| commit | 4ed108352d9b60a723a5071ed05e722826c2b72f | [log] [tgz] |
|---|---|---|
| author | Christian König <christian.koenig@amd.com> | Thu Apr 18 15:25:58 2013 +0200 |
| committer | Alex Deucher <alexander.deucher@amd.com> | Mon Apr 22 10:39:16 2013 -0400 |
| tree | d2f1500ca5a72b79d073770f28916d68d37a91fa | |
| parent | 9054ae1ce33f08315616999c742e6656b9967724 [diff] |
drm/radeon: put UVD PLLs in bypass mode Just power down the PLL when we get a VCLK or DCLK of zero. Enabling the bypass mode early should also allow us to switch UVD clocks on the fly. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>