| commit | 4aa0b5d457f5d29522b5db4aeb4587fc4dc24054 | [log] [tgz] |
|---|---|---|
| author | Mika Kuoppala <mika.kuoppala@linux.intel.com> | Tue Oct 15 18:44:41 2019 +0300 |
| committer | Chris Wilson <chris@chris-wilson.co.uk> | Tue Oct 15 18:15:59 2019 +0100 |
| tree | c8f47049dabe546301b0aae8a9d0957272e87f88 | |
| parent | 62037ffff229b7d94f1db5ef8d2e2ec819832ef3 [diff] |
drm/i915/tgl: Add HDC Pipeline Flush Add hdc pipeline flush to ensure memory state is coherent in L3 when we are done. v2: Flush also in breadcrumbs (Chris) Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-3-mika.kuoppala@linux.intel.com