| commit | 485d531c695b0f5c87180a7724b85322d3967d39 | [log] [tgz] |
|---|---|---|
| author | Alex Deucher <alexander.deucher@amd.com> | Mon Sep 28 14:16:25 2020 -0400 |
| committer | Alex Deucher <alexander.deucher@amd.com> | Tue Sep 29 16:14:03 2020 -0400 |
| tree | cc6e5b7b7d87d00e694278c5589b9933ec11e758 | |
| parent | 808ec542c0297ae0b945ed0e6aba6f625ea2353c [diff] |
drm/amdgpu/swsmu/smu12: fix force clock handling for mclk The state array is in the reverse order compared to other asics (high to low rather than low to high). Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1313 Reviewed-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>