tree 43794dc9e7f8525c9ef0ba8f66b02a3818e3fe36
parent 2aab7a2055a1705c9e30920d95a596226999eb21
author Abhishek Sahu <absahu@codeaurora.org> 1480088488 +0530
committer Stephen Boyd <sboyd@codeaurora.org> 1482364645 -0800

clk: qcom: ipq4019: remove fixed clocks and add pll clocks

The current ipq4019 clock driver registered the PLL clocks and
dividers as fixed clock. These fixed clock needs to be removed
from driver probe function and same need to be registered with
clock framework. These PLL clocks should be programmed only
once and the same are being programmed already by the boot
loader so the set rate operation is not required for these
clocks. Only the rate can be calculated by clock operations
in clock driver file so this patch adds the same.

The PLL takes the reference clock from XO and generates the
intermediate VCO frequency. This VCO frequency will be divided
down by different PLL internal dividers. Some of the PLL
internal dividers are fixed while other are programmable.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>