| commit | 44ce6c3dc8479bb3ed68df13b502b0901675e7d6 | [log] [tgz] |
|---|---|---|
| author | Eric Yang <Eric.Yang2@amd.com> | Fri Nov 15 12:04:25 2019 -0500 |
| committer | Alex Deucher <alexander.deucher@amd.com> | Thu Dec 05 18:23:04 2019 -0500 |
| tree | 45979ce66d0ea9908ce127875dd62ff3e61d781b | |
| parent | dd0b162fd00915728860a360c97752988782b8cc [diff] |
drm/amd/display: update dispclk and dppclk vco frequency Value obtained from DV is not allowing 8k60 CTA mode with DSC to pass, after checking real value being used in hw, find out that correct value is 3600, which will allow that mode. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>