| commit | 52ca14e6844a04e174b5cd3d7dbf63a23271775c | [log] [tgz] |
|---|---|---|
| author | Changbin Du <changbin.du@intel.com> | Tue May 15 10:35:35 2018 +0800 |
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | Mon Jul 09 10:22:50 2018 +0800 |
| tree | 5d21f64cc6f50afc3c4910b573d87d3120aeb0d2 | |
| parent | 6fd7937832698e73a5719ff488c2fc5e22c9c0ba [diff] |
drm/i915/gvt: Handle MMIO GEN8_GAMW_ECO_DEV_RW_IA for 64K GTT The register RENDER_HWS_PGA_GEN7 is renamed to GEN8_GAMW_ECO_DEV_RW_IA from GEN8 which can control IPS enabling. v3: MMIO control for IPS is not removed from gen9 but gen10 (Matthew Auld) v2: IPS of all engines must be enabled together for gen9. Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>