| commit | 3c26d0314c10ceb77511e2cc81894001d488c1d0 | [log] [tgz] |
|---|---|---|
| author | Alex Deucher <alexander.deucher@amd.com> | Mon Sep 28 14:16:25 2020 -0400 |
| committer | Alex Deucher <alexander.deucher@amd.com> | Tue Sep 29 17:09:59 2020 -0400 |
| tree | deae39a868d0aa6cb06bbb325534eae2617ab495 | |
| parent | a39d0d7bdf8c21ac7645c02e9676b5cb2b804c31 [diff] |
drm/amdgpu/swsmu/smu12: fix force clock handling for mclk The state array is in the reverse order compared to other asics (high to low rather than low to high). Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1313 Reviewed-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>