| commit | 33868a91c1d9627b5003b8e299c46c6cfee4ff18 | [log] [tgz] |
|---|---|---|
| author | Madhav Chauhan <madhav.chauhan@intel.com> | Sun Sep 16 16:23:28 2018 +0530 |
| committer | Jani Nikula <jani.nikula@intel.com> | Wed Sep 26 15:52:26 2018 +0300 |
| tree | c7fdd6798fdd4ea25272ac4672b4dc071159a68c | |
| parent | 7a90938332d80faf973fbcffdf6e674e7b8f0914 [diff] |
drm/i915/icl: Define data/clock lanes dphy timing registers This patch defines DSI_CLK_TIMING_PARAM, DPHY_CLK_TIMING_PARAM, DSI_DATA_TIMING_PARAM, DPHY_DATA_TIMING_PARAM register used in dphy programming. v2: Define mask/shift for bitfields and keep names as per BSPEC (Jani N) Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1537095223-5184-6-git-send-email-madhav.chauhan@intel.com